This invention relates to field-programmable gate arrays (“FPGAs”), such as those of the type known as programmable logic devices (“PLDs”). More particularly, the invention relates to transceiver circuitry for inclusion in such devices.
For convenience herein, all programmable integrated circuit devices to which the invention can be applied will be referred to as FPGAs.
A frequent objective in the manufacture of FPGAs is to give the device a wide range of operating capabilities so that the FPGA can meet the various needs of many different users and thereby create a large market for the FPGA product. In general, the larger the market, the lower the unit cost the FPGA can have. On the other hand, giving an FPGA too many capabilities puts upward pressure on unit cost, so it is necessary to strike a balance between a set of capabilities that is large enough to make the product widely usable, without providing such an excess of capabilities that unit cost begins to adversely impact sales volume.
In recent years sophisticated transceiver circuitry has been added to many FPGAs. For example, such transceiver circuitry may be used to support high-speed serial data communication to and/or from the FPGA. Such circuitry may sometimes be referred to as high-speed serial interface (“HSSI”) circuitry. This circuitry may include some components that are hard-wired or partly hard-wired to perform particular transceiver tasks. Certain aspects of these components or their operation may be programmable. The transceiver circuitry on an FPGA typically communicates with the “core” (i.e., the basic programmable logic circuitry) of the FPGA. Examples of HSSI circuitry on FPGAs are shown in Lee et al. U.S. Pat. No. 6,650,140.
Data rates are constantly increasing, and so there is constant interest in increasing the data rates that FPGA transceivers can support. On the other hand, many FPGA users continue to be interested in using lower date rates. This creates a demand for FPGA transceivers that can operate over a very wide range of frequencies (e.g., from the relatively slow frequencies that were developed some time ago to the much higher frequencies that are at the constantly advancing leading edge). For example, it might be desirable for FPGA transceiver circuitry to be able to support data rates from 622 Mbps to 12 Gbps (i.e., from 622 mega-bits per second to 12 giga-bits per second). Moreover, it might be desirable for the FPGA transceiver circuitry to be able to support any or substantially any data rate within this range. (It will be understood that all data rates and/or frequencies mentioned herein are only examples, and that the invention is not limited to any particular data rates, range of data rates, frequencies, or range of frequencies.)